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DA6180.001 27 December, 2006
MAS6180
AM Receiver IC
* * * * * * * *
DESCRIPTION
The MAS6180 AM-Receiver chip is a highly sensitive, simple to use AM receiver specially intended to receive time signals in the frequency range from 40 kHz to 100 kHz. Only a few external components are required for time signal receiver. The circuit has preamplifier, wide range automatic gain control, demodulator and output comparator built in. The output signal can be processed directly by an additional digital circuitry to extract the data from the received signal. The control for AGC (automatic gain control) can be used to switch AGC on or off if necessary. MAS6180 has options for compensating shunt capacitances of different crystals (See ordering information on page 9).
Single Band Receiver IC High Sensitivity Very Low Power Consumption Wide Supply Voltage Range Power Down Control Control for AGC On High Selectivity by Crystal Filter Fast Startup Feature
FEATURES
* * * * * * * * * * * * Single Band Receiver IC Highly Sensitive AM Receiver, 0.4 VRMS typ. Wide Supply Voltage Range from 1.1 V to 3.6 V Very Low Power Consumption Power Down Control Fast Startup Only a Few External Components Necessary Control for AGC On Wide Frequency Range from 40 kHz to 100 kHz High Selectivity by Quartz Crystal Filter Crystal Compensation Capacitance Options Differential Input
APPLICATIONS
* Single Band Time Signal Receiver WWVB (USA), JJY (Japan), DCF77 (Germany), MSF (UK), HGB (Switzerland) and BPC (China)
BLOCK DIAGRAM
VDD
QOP
QI
QOM
AON Demodulator & Comparator OUT
RFIP
VDD
AGC Amplifier
RFIM
Power Supply/Biasing VDD VSS PDN AGC DEC
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DA6180.001 27 December, 2006
MAS6180 PAD LAYOUT
VSS pad bonded first!
1070 m
VDD QOP QOM QI AGC OUT VSS RFIM RFIP PDN AON DEC
MAS6180Ax, x = 1, 2, 5
DIE size = 1.07 mm x 1.37 mm; PAD size = 80 m x 80 m Note: Because the substrate of the die is internally connected to VSS, the die has to be connected to VSS or left floating. Please make sure that VSS is the first pad to be bonded. Pick-and-place and all component assembly are recommended to be performed in ESD protected area. Note: Coordinates are pad center points where origin has been located in bottom-left corner of the silicon die. Pad Identification Power Supply Voltage Positive Quartz Filter Output for Crystal Negative Quartz Filter Output for Crystal Quartz Filter Input for Crystal and External Compensation Capacitor AGC Capacitor Receiver Output Demodulator Capacitor AGC On Control Power Down Positive Receiver Input Negative Receiver Input Power Supply Ground Name VDD QOP QOM QI AGC OUT DEC AON PDN RFIP RFIM VSS X-coordinate 152 m 152 m 152 m 152 m 152 m 152 m 915 m 915 m 915 m 915 m 915 m 915 m Y-coordinate 1137 m 1002 m 815 m 629 m 443 m 257 m 265 m 451 m 636 m 824 m 1010 m 1158 m Note
1370 m
1
2 3 4 5 5
Notes: 1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor. 2) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 A - at power down the output is pulled to VSS (pull down switch) 3) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 A which is switched off at power down 4) PDN = VSS means receiver on; PDN = VDD means receiver off Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 5) Receiver inputs RFIP and RFIM have both 600 k biasing resistors towards VDD
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DA6180.001 27 December, 2006
6)
ABSOLUTE MAXIMUM RATINGS
All Voltages with Respect to Ground
Parameter Supply Voltage Input Voltage ESD Rating
Symbol VDD-VSS VIN VESD
Conditions
Min - 0.3 VSS-0.3 2
Max 5.5 VDD+0.3
Unit V V kV
Latchup Current Limit
ILUT
For all pins, Human Body Model (HBM), ESD Association Standard Test Method ESD-STM5.11998, CESD = 100 pF, Rs = 1500 ), For all pins, test according to Micro Analog Systems specification ESQ0141. See note below.
100
mA
Operating Temperature Storage Temperature
TOP TST
-40 - 55
+85 +150
C C
Stresses beyond those listed may cause permanent damage to the device. The device may not operate under these conditions, but it will not be destroyed. Note: In latchup testing the supply voltages are connected normally to the tested device. Then pulsed test current is fed to each input separately and device current consumption is observed. If the device current consumption increases suddenly due to test current pulses and the abnormally high current consumption continues after test current pulses are cut off then the device has gone to latch up. Current pulse is turned on for 10 ms and off for 20 ms.
ELECTRICAL CHARACTERISTICS
Operating Conditions: VDD = 1.5V, Temperature = 25 unless otherwise specified. C,
Parameter Operating Voltage Current Consumption
Symbol VDD IDD
Conditions VDD=1.5 V, Vin=0 Vrms VDD=1.5 V, Vin=20 mVrms VDD=3.6 V, Vin=0 Vrms VDD=3.6 V, Vin=20 mVrms See note below.
Min 1.10 40 24
Typ 55 40 58 43
Max 3.6 80 65
Unit V A
Stand-By Current Input Frequency Range Minimum Input Voltage Maximum Input Voltage Receiver Input Resistance Receiver Input Capacitance Input Levels |lIN|<0.5 A Output Current VOL<0.2 VDD;VOH >0.8 VDD Output Pulse
IDDoff fIN VIN min VIN max RRFI CRFI VIL VIH |IOUT| T100ms T200ms T500ms T800ms
40 0.4 20 Differential Input, f=40 kHz..77.5 kHz VDD-0.35 5 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms 1 Vrms VIN 20 mVrms Fast Start-up, Vin=0.4 Vrms Fast Start-up, Vin=20 mVrms 50 150 400 700 500 800 1.3 3.5 50 600 0.5
0.1 100 1
A kHz Vrms mVrms k pF V A
0.35
140 230 600 900
ms ms ms ms s
Startup Time Output Delay Time
TStart TDelay
100
ms
Note: Stand-by current consumption may increase if V IH and V IL differ from VDD and 0 respectively.
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DA6180.001 27 December, 2006
TYPICAL APPLICATION
Note 1
MAS6180A1, A2
VDD
Note 4 Optional Control for AGC on/hold QI QOM AON Demodulator & Comparator OUT Receiver Output
Note 5 RFIP Ferrite Antenna
VDD
QOP
AGC Amplifier
RFIM
VDD
Power Supply/Biasing VDD VSS PDN AGC CAGC 10 F VDD DEC CDEC 47 nF VDD VDD AGC CAGC + 10 F Note 2 DEC CDEC 47 nF
1.4 V GND
OR
Note 3 Power Down / Fast Startup Control
Note 2
Figure 1. Application circuit of internal compensation capacitance option version MAS6180A1 and A2.
Note 1 CC_EXT=C0
MAS6180A5
VDD
Note 4 Optional Control for AGC on/hold AON Demodulator & Comparator OUT Receiver Output
Note 5 RFIP Ferrite Antenna
VDD
QOP
QI
QOM
AGC Amplifier
RFIM
VDD
Power Supply/Biasing VDD VSS PDN AGC CAGC 10 F DEC CDEC 47 nF VDD VDD AGC CAGC + 10 F Note 2 Note 2 DEC CDEC 47 nF
1.4 V GND VDD
OR
Note 3 Power Down / Fast Startup Control
Figure 2. Application circuit of external compensation capacitance option version MAS6180A5.
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DA6180.001 27 December, 2006
TYPICAL APPLICATION (Continued)
Note 1 Note 4 Optional Control for AGC on/hold QI QOM AON Demodulator & Comparator OUT Receiver Output
MAS6180A5
VDD
Note 5 RFIP Ferrite Antenna
VDD
QOP
AGC Amplifier
RFIM
Antenna Frequency Selection VDD
Power Supply/Biasing VDD VSS PDN AGC CAGC 10 F DEC CDEC 47 nF AGC CAGC 10 F + DEC CDEC 47 nF
OR
1.4 V GND
VDD
Note 3 Power Down / Fast Startup Control
Note 2 VDD VDD Note 2
Figure 3. Dual band application circuit of external compensation capacitance option version MAS6180A5. PMOS switch transistor is used since RFIM input is biased close to VDD voltage.
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DA6180.001 27 December, 2006
TYPICAL APPLICATION (Continued)
Note 1: Crystals The crystal as well as ferrite antenna frequencies are chosen according to the time-signal system (Table 1). The crystal shunt capacitance C0 should be matched as well as possible with the internal shunt capacitance compensation capacitor CC of MAS6180. MAS6180A5 is option for external crystal compensation capacitor. The external compensation capacitor should be matched similarly as well as possible with crystal's shunt capacitance. See Compensation Capacitance Options on table 2. Table 1. Time-Signal System Frequencies Time-Signal System Location DCF77 HGB MSF WWVB JJY BPC Germany Switzerland United Kingdom USA Japan China
Antenna Frequency 77.5 kHz 75 kHz 60 kHz 60 kHz 40 kHz and 60 kHz 68.5 kHz
Recommended Crystal Frequency 77.503 kHz 75.003 kHz 60.003 kHz 60.003 kHz 40.003 kHz and 60.003 kHz 68.505 kHz
Table 2 . Compensation Capacitance Options Crystal Description Device CC MAS6180A1 MAS6180A2 MAS6180A5 0.75 pF 1.3 pF CC_EXT For low C0 crystals For high C0 crystals For any crystals, external compensation capacitor
It should be noted that grounded crystal package has reduced shunt capacitance. This value is about 85% of floating crystal shunt capacitance. For example crystal with 1 pF floating package shunt capacitance can have 0.85 pF grounded package shunt capacitance. PCB traces of crystal and external compensation capacitance should be kept at minimum to minimize additional parasitic capacitance which can cause capacitance mismatching. In dual band receiver configuration the crystals can be connected in parallel thus external compensation capacitor value CC_EXT must be sum of two crystals' shunt capacitances. Instead of parallel crystal connection it is also possible to connect other crystal from QOP pin and the other crystal from QOM pin to common QI pin (figure 3). In this circuit configuration no external compensation capacitor is required since the crystals compensate each other. The sensitivity of dual band receiver configuration will be lower than that of single band receiver configuration since the noise band width of crystal filter with two parallel crystals is double. Table 3 below presents some crystal manufacturers having suitable crystals for timesignal receiver application. Table 3. Crystal Manufacturers and Crystal Types in Alphaphetical Order for Timesignal Receiver Application Manufacturer Crystal Type Dimensions Web Link Citizen Epson Toyocom KDS Daishinku Microcrystal Seiko Instruments CFV-206 C-2-Type C-4-Type DT-261 MX1V-L2N MX1V-T1K VTC-120 o 2.0 x 6.0 o 1.5 x 5.0 o 2.0 x 6.0 o 2.0 x 6.0 o 2.0 x 6.0 o 2.0 x 8.1 o 1.2 x 4.7 http://www.citizen.co.jp/tokuhan/quartz/ http://www.epsontoyocom.co.jp/english/ http://www.kds.info/index_en.htm http://www.microcrystal.com/ http://www.sii-crystal.com
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DA6180.001 27 December, 2006
TYPICAL APPLICATION (Continued)
Note 2: AGC Capacitor The AGC and DEC capacitors must have low leakage currents due to very small signal currents through the capacitors. The insulation resistance of these capacitors should be at minimum 100 M. Also probes with at least few 100 M impedance should be used for voltage probing of the AGC and DEC pins. Electrolytic AGC capacitor should have voltage rating at least 25 V for low enough leakage. DEC capacitor can be low leakage chip capacitor. Both the AGC and DEC capacitors can be connected either to VDD or to VSS. To minimize leakage currents during power down the AGC and DEC capacitors are best to be connected to VDD since in power down the AGC and DEC pins go to VDD voltage potential. In this case the positive polarity pin of electrolyte capacitor should be connected to VDD. If the capacitors are connected to VSS then the negative polarity pin of electrolyte capacitor should be connected to VSS. Note 3: Power Down / Fast Startup Control Both power down and fast startup are controlled using the PDN pin. The device is in power down (turned off) if PDN = VDD and in power up (turned on) if PDN = VSS. Fast startup is triggered automatically by the falling edge of PDN signal, i.e., controlling device from power down to power up. The VDD must be high before falling edge of PDN to guarantee proper operation of fast startup circuitry. Before power up the device should have been kept in power down state at least 50ms. This guarantees that the AGC capacitor voltage has been completely pulled to VDD during power down. The startup time without proper fast startup control can be several minutes but with fast startup it is shortened typically to few seconds. Note 4: Optional Control for AGC On/Hold AON control pin has internal pull up which turns AGC circuit on all the time if AON pin is left unconnected. Optionally AON control can be used to hold and release AGC circuit. Stepper motor drive of analog clock or watch can produce disturbing amount of noise which can shift the input amplifier gain to unoptimal level. This can be avoided by controlling AGC hold (AON=VSS) during stepper motor drive periods and releasing AGC (AON=VDD) when motors are not driven. The AGC should be in hold only during disturbances and kept on other time released since due to leakage the AGC can change slowly when in hold. Note 5: Ferrite Antenna The ferrite antenna converts the transmitted radio wave into a voltage signal. It has an important role in determining receiver performance. Recommended antenna impedance at resonance is around 150 k. Low antenna impedance corresponds to low noise but often also to small signal amplitude. On the other hand high antenna impedance corresponds to high noise but also large signal. The optimum performance where signal-to-noise ratio is at maximum is achieved in between. The antenna should have also some selectivity for rejecting near signal band disturbances. This is determined by the antenna quality factor which should be approximately 100. Much higher quality factor antennas suffer from extensive tuning accuracy requirements and possible tuning drifts by the temperature. Antenna impedance can be calculated using equation 1 where f0, L, Qant and C are resonance frequency, coil inductance, antenna quality factor and antenna tuning capacitor respectively. Antenna quality factor Qant is defined by ratio of resonance frequency f0 and antenna bandwidth B (equation 2).
Rantenna = 2 f 0 L Qantenna =
Qantenna = f0 B
Qantenna 1 = 2 f 0 C 2 B C
Equation 1.
Equation 2.
Table 4 below presents some antenna manufacturers for time signal application. Table 4. Antenna Manufacturers and Antenna Types in Alphaphetical Order for Time Signal Application Manufacturer Antenna Type Dimensions Web Link HR Electronic GmbH Sumida 60716 (60kHz) 60708 (77.5kHz) ACL80A/B (40kHz, 60kHz) ACL27 (40kHz, 60kHz) o 10 x 60 mm o 14 x 83 mm 6 x 7.3 x 28 mm http://www.hrelectronic.com/ www.sumida.co.jp/jeita/XJA021.pdf
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DA6180.001 27 December, 2006
MAS6180 SAMPLES IN SBDIL 20 PACKAGE
1 VDD 2 3 QOP 4 QOM 5 6 QI 7 AGC 8 9 OUT 10
MAS6180ZZ YYWW XXXXX.X
20 VSS 19 18 RFIM 17 RFIP 16 15 14 PDN 13 AON 12 DEC 11
Top Marking Definitions: YYWW = Year Week XXXXX.X = Lot Number ZZ =Sample Version
PIN DESCRIPTION
Pin Name VDD QOP QOM Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Type NC P NC AO NC NC AI AO NC DO NC AO DI DI NC NC AI AI NC G Function Positive Power Supply Positive Quartz Filter Output for Crystal Negative Quartz Filter Output for External Compensation Capacitor or Second Crystal Quartz Filter Input for Crystal and External Compensation Capacitor AGC Capacitor Receiver Output Demodulator Capacitor AGC On Control Power Down Input 3 Note
1 2
QI AGC OUT DEC AON PDN
4 5
RFIP RFIM VSS
Positive Receiver Input Negative Receiver Input Power Supply Ground
6 6
A = Analog, D = Digital, P = Power, G = Ground, I = Input, O = Output, NC = Not Connected
Notes: 1) External crystal compensation capacitor pin QOM is connected only in MAS6180A5 version. It is left unconnected in MAS6180A1 and A2 versions which have internal compensation capacitor. 2) Pin 6 between QOM and QI must be connected to VSS to eliminate DIL package lead frame parasitic capacitances disturbing the crystal filter performance. All other NC (Not Connected) type pins are also recommended to be connected to VSS to minimize noise coupling. 3) OUT = VSS when carrier amplitude at maximum; OUT = VDD when carrier amplitude is reduced (modulated) - the output is a current source/sink with |IOUT| > 5 A - at power down the output is pulled to VSS (pull down switch) 4) AON = VSS means AGC off (hold current gain level); AON = VDD means AGC on (working) - Internal pull-up with current < 1 A which is switched off at power down 5) PDN = VSS means receiver on; PDN = VDD means receiver off - Fast start-up is triggered when the receiver is after power down (PDN=VDD) controlled to power up (PDN=VSS) i.e. at the falling edge of PDN signal. 6) Receiver inputs RFIP and RFIM have both 600 k biasing resistors towards VDD
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DA6180.001 27 December, 2006
ORDERING INFORMATION
Product Code MAS6180A1TC00 Product Single Band AM-Receiver IC with Differential Input Single Band AM-Receiver IC with Differential Input Single Band AM-Receiver IC with Differential Input Description EWS-tested wafer, diameter 150 mm, thickness 400 m. EWS-tested wafer, diameter 150 mm, thickness 400 m. EWS-tested wafer, diameter 150 mm, thickness 400 m. Capacitance Option CC = 0.75 pF CC = 1.3 pF External compensation capacitor
MAS6180A2TC00
MAS6180A5TC00
Contact Micro Analog Systems Oy for other wafer thickness options. N The formation of product code An example for MAS6180A1TC00: MAS6180 A 1 Product Design Capacitance option: name version CC = 0.75 pF TC Package type: TC = 400 m thick EWS tested wafer 00 Delivery format: 00 = bare wafer 05 = dies on tray
LOCAL DISTRIBUTOR
MICRO ANALOG SYSTEMS OY CONTACTS
Micro Analog Systems Oy Kamreerintie 2, P.O. Box 51 FIN-02771 Espoo, FINLAND Tel. +358 9 80 521 Fax +358 9 805 3213 http://www.mas-oy.com
NOTICE Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that the circuits are free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes no claim or warranty that such applications will be suitable for the use specified without further testing or modification.
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